The present invention relates generally to improvements to array processing, and more particularly, to advantageous techniques for providing dual mode operation of a processor as both a control element for an array and as a processing element in the array.
Separate control and processing elements are seen in a variety of parallel processing arrays. Such elements are typically dedicated to defined control or processing tasks. Various aspects of such arrangements result in overall system inefficiencies.
The present invention recognizes that typically in the prior art when a Single Instruction Multiple Data stream (SIMD) instruction is executed, only the array""s Processing Element""s (PE""s) resources are used, except for the controller Sequence Processor""s (SP""s) address generation resources, and when a Single Instruction Single Data (SISD) instruction is executed, only the controller SP""s resources are used thereby keeping the controller resources separate from the SIMD array resources. The present invention advantageously combines a PE and the controller SP into a single device, eliminates a dedicated PE-to-SP data bus by taking advantage of this fact, and allows the combined unit to share a single set of execution units thereby reducing implementation costs. With the present invention, an SP controller SISD instruction can be executed in parallel with a SIMD PE instruction.
These and other features, aspects and advantages of the invention will be apparent to those of skill in the art from the following detailed description taken together with the accompanying drawings.